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The EFM/EFM+bit stream and bit clock are then output to DPU for channel bit processing. DPU Data path unit (DPU) provides protection on data with lost synchronization patterns and demodulates EFM/EFM+ bit stream into the channel raw data that will be corrected by the decoder. The synchronization protection makes data after the synchronization pattern to be extracted even if the synchronization pattern is not found. Spindle Controller The spindle controller is used to control disc spindle motor.

5V can be controlled by digital inputs of 0V to 5V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD -VSS and VDD -VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic “1” is present at the inhibit input terminal, all channels are off. [ /Title (CD405 1B, CD4052 B, CD4053 B) /Subject (CMOS Analog Multi- The CD4051B is a single 8-Channel multiplexer having three plexbinary control inputs, A, B, and C, and an inhibit input.

In addition, it accepts an special WARP mode, which inserts one programmable RLC code in the bitmap to reduce the image size stored in DRAM. It also features automatic shadow/outline generation in 2-color mode, 2 Hilight areas, 1 ChangeColor area and 1 OSDVoid area. One OSD area can occupy the full or a partial screen, or multiple OSDs can occur in a screen at the same time, only if they don't occupy the same horizontal line. The output image is blended with the video-SPU mixed stream. Cursor A hardware cursor generator is integrated in Video Ou tput Unit.

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