By Ron Hogervorst
Design of Low-Voltage, Low-Power CMOS Operational Amplifier Cells describes the idea and layout of the circuit components which are required to achieve a low-voltage, low-power operational amplifier. those components comprise constant-gm rail-to-rail enter phases, class-AB rail-to-rail output levels and frequency repayment equipment. a number of examples of every of those circuit parts are investigated. additionally, the ebook illustrates a number of silicon realizations, giving their dimension effects.
The textual content specializes in compact low-voltage low-power operational amplifiers with strong functionality. Six uncomplicated high-performance class-AB amplifiers are learned utilizing a really compact topology making them relatively compatible to be used as VLSI library cells. all the designs can use a provide voltage as little as 3V. one of many amplifier designs dissipates simply 50µW with a solidarity achieve frequency of 1.5 MHz. A moment set of amplifiers run on a provide voltage somewhat above 1V. The amplifiers mix a low strength intake with a achieve of a hundred and twenty dB. furthermore, the layout of 3 totally differential operational amplifiers is addressed.
Design of Low-Voltage, Low-Power CMOS Operational Amplifier Cells is meant for pro designers of analog circuits. it's also appropriate to be used as a textual content e-book for a sophisticated direction in CMOS operational amplifier design.
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Extra resources for Design of Low-Voltage, Low-Power Operational Amplifier Cells
The effective gate -source voltage ofthe input transistors as small as possible. • The W over L ratio ofthe current mirror and the current sources as small as possible. The thermal noise can be minimized by making: • The gm of the input transistors as large as possible. • The W over L ratio ofthe current mirror and the current sources as small as possible. The flicker noise of the input stage can be minimized by making: • The area of the input transistors as large as possible. • The length ofthe current mirror and the current sources as long as possible.
L 1,2 and LS,6 are 2 ~, and L ll ,12 is 4 ~. From this data, it can be calculated that the total flicker noise voltage is about three times that of the input transistors. The above offset and noise analyses have been performed using a P-channel input stage. Evidently, the analyses can be repeated for a folded cascoded input stage with N-channel input transistors. However, the use of P-channel input devices is preferred in most processes, because they tend to display a lower flicker noise component [1, 6].
This, in turn, causes an undesired additional distortion. To understand this, consider the non-inverting feedback application, as shown in figure 3-7. The gain of this configuration is given by (3-21) As can be concluded from this expression, a varying loop gain, A~, results in a change of the gain of the non-inverting feedback configuration. At heavy resistive loads, the nominal value of A~ can be as low as 100 in the upper and lower part of the common-mode input range . At intermediate common-mode input voltages the gain increases to a value of 200.