By Benoit Nadeau-Dostie
Layout for AT-Speed try, prognosis and dimension is the 1st e-book to supply functional and confirmed design-for-testability (DFT) ideas to chip and procedure layout engineers, try out engineers and product managers on the silicon point in addition to on the board and structures degrees. Designers will see how the implementation of embedded try allows simplification of silicon debug and process bring-up. attempt engineers will make sure how embedded attempt offers a high-quality point of at-speed try, prognosis and dimension with out exceeding the functions in their apparatus. Product managers will find out how the time, assets and prices linked to try improvement, manufacture price and lifecycle upkeep in their items could be considerably diminished by way of designing embedded try within the product. A entire layout circulate and research of the influence of embedded try out on a layout makes this ebook a `must learn' prior to any DFT is tried.
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Extra resources for Design for AT-Speed Test, Diagnosis and Measurement (FRONTIERS IN ELECTRONIC TESTING Volume 15)
The coupling faults are usually covered by repeating a march test with different foreground and background patterns. The serial memory BIST approach allows the design engineer to trade off test time for area by dividing up the word in slices of equal size. In fact, the design engineer can revert to a fully parallel approach if it makes sense for the application. This trade-off is explained in more detail in the section “Embedded Test for Multiple Memories” on page 46. BIST for Embedded Memories 41 Description of Controllers This section introduces the memory BIST architecture, the various architectural components, the supported memory test configurations, and the memory BIST operating protocol.
Once generated, the combinational logic tests can be applied by shifting inputs and outputs via the scan chain. Scan design also enables other DFT methods such as BIST, because it provides a simple mechanism for applying and collecting test patterns and results. Another advantage is that a scan circuit is inherently easy to diagnose. This feature is invaluable when a root-cause analysis of test failures is required, whether for external test or BIST. Scan Styles Although there are different scan design styles, multiplexed scan is the most popular style and the only one discussed in detail in this book.
A tester loads these limits serially. The binary-encoded measurement results are serially shifted out, together with a pass/fail bit for each limit. pllBIST measures the peak-to-peak and/or RMS jitter. The cumulative distribution function (CDF) limits for the jitter (0 to 100 percent for peak-to-peak; 16 to 84 percent for RMS) are loaded in at test time from off chip or are hard-wired on chip. By loading in various limits, the entire CDF can be measured for rapid, low-cost characterization. pllBIST implements an all-digital BIST circuit that fully tests PLLs at application speed.